Chip #

Represents integrated circuits from simple logic gates to complex microcontrollers. Breadpad uses SPICE subcircuits to model chip behavior, supporting DIP packages from 8 to 48 pins.

Basic Properties #

Package: DIP (Dual In-line Package)
SPICE Designation: X (subcircuit)
Pin Counts: 8, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 42, 48
Layout: Spans breadboard gap, pins on rows 7 and 9

Key Features #

Pin Configuration #

Pin Numbering: Counter-clockwise from top-left
Pin 1 Marker: Usually indicated by dot or notch
Power Pins: Typically corner pins (varies by chip)
Custom Labels: Assignable pin names

SPICE Subcircuit (Premium Feature) #

Import complete SPICE models
Define custom behavior
Hierarchical design support
Vendor-provided models

SPICE Netlist Format #

Basic IC instance:

.SUBCKT 74HC00_MODEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14
* Subcircuit definition here
.ENDS

X1 pin1 pin2 pin3 ... pin14 74HC00_MODEL

Common IC Categories #

Logic Gates (74 Series) #

74HC00 - Quad NAND

14 pins
4 independent NAND gates
VCC on pin 14, GND on pin 7

74HC04 - Hex Inverter

14 pins
6 independent inverters
Popular for oscillators

74HC74 - Dual D Flip-Flop

14 pins
2 flip-flops with preset/clear
Edge-triggered

Operational Amplifiers #

LM358 - Dual Op-Amp

8 pins
2 independent op-amps
Single supply capable

TL072 - Dual JFET Op-Amp

8 pins
Low noise, high impedance
Audio applications

LM324 - Quad Op-Amp

14 pins
4 independent op-amps
Wide supply range

Timer ICs #

NE555 - Timer

8 pins
Astable/monostable/bistable
Most popular timer IC

LM556 - Dual Timer

14 pins
Two 555 timers
Independent operation

Voltage Regulators #

LM7805 - 5V Regulator

TO-220 package (3 pins)
1A output current
Thermal protection

LM317 - Adjustable Regulator

TO-220 package (3 pins)
1.25V to 37V output
Current limiting

Microcontrollers #

ATtiny85

8 pins
6 I/O pins
Internal oscillator

PIC16F84A

18 pins
13 I/O pins
Flash memory

Creating Custom Subcircuits #

Basic Template #

.SUBCKT MYIC VCC GND IN1 IN2 OUT1 OUT2
* Power supply connections
RVCC VCC VCCINT 0.1
RGND GND GNDINT 0.1

* Internal circuitry
* Add your components here

.ENDS MYIC

Logic Gate Example #

.SUBCKT NAND2 A B Y VCC GND
* Input protection
D1 A VCC DMOD
D2 GND A DMOD
D3 B VCC DMOD  
D4 GND B DMOD

* NAND logic using transistors
MP1 Y A VCC VCC PMOS W=10u L=1u
MP2 Y B VCC VCC PMOS W=10u L=1u
MN1 Y A N1 GND NMOS W=5u L=1u
MN2 N1 B GND GND NMOS W=5u L=1u

.MODEL DMOD D
.MODEL PMOS PMOS
.MODEL NMOS NMOS
.ENDS NAND2

Op-Amp Macromodel #

.SUBCKT OPAMP INP INN OUT VCC VEE
* Simplified op-amp model
* Input stage
RIN INP INN 10MEG
G1 0 N1 INP INN 100

* Frequency compensation
R1 N1 N2 1K
C1 N2 0 159n

* Output stage  
E1 OUT 0 N2 0 1
.ENDS OPAMP

Pin Layout Guidelines #

Standard DIP Spacing #

Pin pitch: 0.1" (2.54mm)
Row spacing: 0.3" (7.62mm) for narrow
Row spacing: 0.6" (15.24mm) for wide

Power Pin Conventions #

8-pin: VCC=8, GND=4 (op-amps)
14-pin: VCC=14, GND=7 (logic)
16-pin: VCC=16, GND=8
Exceptions: Always check datasheet

Using Vendor Models #

Download SPICE model from manufacturer
Check syntax - may need conversion
Import subcircuit into Breadpad
Verify pin mapping matches package
Test basic functionality before complex circuits

Common Issues and Solutions #

Convergence Problems #

Add small capacitors to high-impedance nodes
Use .NODESET for initial voltages
Increase ITL1, ITL2 parameters

Model Complexity #

Start with simplified models
Add complexity as needed
Balance accuracy vs. simulation speed

Power Supply Bypass #

Always add 0.1µF ceramic near VCC
Add bulk capacitance for multiple ICs
Short, direct ground connections

Design Tips #

Decoupling: 0.1µF ceramic per IC minimum
Logic Families: Don’t mix without level shifters
Unused Inputs: Tie to VCC or GND
Unused Gates: Connect inputs together
ESD Protection: Add input protection diodes
Thermal: Consider power dissipation