/* Original arithmetic-contract workbench, not a vendor MCU timing model.
 * Commands at RAM +0,+4 are little-endian words but LBU reads their low bytes.
 * +8 selects 0:widened unsigned sum, 1:wrap to u8, 2:saturate to u8,
 * 3:interpret the low byte as i8. Other modes fail closed with status 1.
 * +32 is the request sequence, +36 the last acknowledged sequence.
 * Publish commands first, then change +32. One host transaction per word.
 * Results +12 widened sum, +16 low byte, +20 selected encoding,
 * +24 sampled mtime, +28 status. GPIO0 uses signed selected >=128.
 * All arithmetic is RV32I; an 8-bit policy does not emulate an 8-bit CPU. */
    .option norvc
    .option norelax
    .section .text.start,"ax",@progbits
    .globl _start
    .type _start,@function
_start:
    lui x5, 0x40000
    addi x6, zero, 1
    sw x6, 8(x5)
    lui x7, 0x20000
    addi x16, zero, 0
poll:
    lw x8, 32(x7)
    beq x8, x16, poll
    addi x16, x8, 0
    lbu x10, 0(x7)
    lbu x11, 4(x7)
    lw x12, 8(x7)
    add x13, x10, x11
    sw x13, 12(x7)
    andi x14, x13, 255
    sw x14, 16(x7)
    addi x15, x13, 0
    sltiu x17, x12, 4
    beq x17, zero, invalid
    beq x12, zero, publish
    addi x17, zero, 1
    beq x12, x17, wrap
    addi x17, zero, 2
    bne x12, x17, signed_byte
    addi x17, zero, 255
    bltu x15, x17, publish
    addi x15, x17, 0
    jal zero, publish
wrap:
    addi x15, x14, 0
    jal zero, publish
signed_byte:
    slli x15, x14, 24
    srai x15, x15, 24
publish:
    sw zero, 28(x7)
    jal zero, result
invalid:
    addi x15, zero, 0
    addi x17, zero, 1
    sw x17, 28(x7)
result:
    sw x15, 20(x7)
    lw x18, 256(x5)
    sw x18, 24(x7)
    addi x19, zero, 128
    slt x19, x15, x19
    xori x19, x19, 1
    sw x19, 4(x5)
    sw x16, 36(x7)
    jal zero, poll
    .size _start, .-_start
    .section .data,"aw",@progbits
    .balign 4
    .word 200,100,0,0,0,0,0,0,1,0
    .section .note.GNU-stack,"",@progbits