Settings clear only the counter. Gates follow the accepted grid, with at most one million samples. Counter settings survive circuit Reset and lesson loads; Apply unchanged settings retains the current gate.

Pulse counter awaits accepted samples.

Counter history awaits completed accepted gates.

Default 0.8 / 2 V hysteresis and 100 ms gate. Actual gates follow the accepted sample grid; no interpolated hardware timing.

Spectrum awaits accepted samples.

8192-sample rectangular records. Mean and leakage retained; not calibrated SNR, noise density or ADC accuracy.

Pause at an accepted analog point to start a new record.

Start clears the completed and partial spectrum record. The next 8192 accepted probe samples form the new record; the current point is excluded. Circuit state, source targets, capacitor histories, time, scope and interval meter stay unchanged. Original JSON copies both channels without interpolation, mean removal or added zeros; an unavailable channel is null. Timing and probes belong to that record; load, source and restart ownership must be retained separately. No stationarity or noise density is inferred.

Analysis options analyse the most recent samples of the completed record. Hann reduces distant leakage but widens tones; its CSV separates coherent-tone amplitude, raw power and power density. These options do not change acquisition. Download or Plot explicitly applies them to the completed record.

Await a valid completed record.

Uses all 8192 raw accepted samples from one completed two-probe record. CH1−CH2 is formed at each simultaneous sample before segment mean removal, windowing and FFT. Periodogram powers are normalized by window power gain and averaged over disjoint segments. This retains channel phase/correlation; it does not subtract independent instrument-floor powers. A selected missing channel refuses rather than being filled with zero.

Choose interior bins, excluding DC and Nyquist. The selected whole-bin sum contains any tones, ripple, noise and leakage in that finite record. Segment means are removed; a small selected-band result does not bound DC error or power outside the band. Shorter segments change resolution and averaging. Rectangular power gain is 1; periodic Hann is 3/8. The bin width and integrated whole-bin width are discrete record quantities, not an analog brick-wall filter or a calibrated measurement bandwidth.

JSON includes both original channel arrays (an unavailable unused channel remains null), probe sockets, record identity, acquisition timing and all averaged bin powers. Analysis does not advance the circuit or alter records. Settings, a new completed record or a cleared owner invalidate the displayed result. This signal-power tool does not infer a noise distribution, SNR, ENOB, confidence interval or converter accuracy.

Await a valid completed spectrum.

Uses all 8192 accepted samples in equal disjoint segments. Segment means are removed before windowing; periodograms are averaged in power. Choose interior bins, excluding DC and Nyquist. Hann can retain near-DC leakage; bin 1 is affected by segment mean removal. Integrated whole-bin width is not an analog brick-wall filter. Shorter segments trade frequency resolution for more averages; averages are not guaranteed independent for colored or correlated data.

Use noise-only records and a known constant gain across the selected band. Optional CH2 subtraction assumes its power equals the independent instrument noise added to CH1. A nonpositive difference is unresolved, not zero device noise. There is no automatic gain calibration, noise identification, floor matching, uncertainty interval or signal/noise separation. Controls analyse a completed record only and do not change the circuit or acquisition.

Isolated DC mode solves a private bias from explicit DC source definitions and reports probe bias voltages. It does not charge live capacitors or accept pending source targets into the transient. Frozen native device/noise models, generic amplifier derivatives and declared internal poles, ideal capacitors/inductors, algebraic ideal transformers, local conservative dλ/dI and admitted Q(V) derivatives; no intrinsic semiconductor charge or semiconductor flicker, correlation, material-noise calibration or stability certification.

Pause an ordinary native circuit. Use an accepted settled point or choose an isolated DC bias.

This is a physical small-signal network calculation about the selected accepted or isolated DC bias, separate from sampled transient noise. It includes resistor 4kT/R current noise, declared saturated MOSFET/JFET channel 4kT·coefficient·gm and, for JFETs, bidirectional gate-junction shot noise. Forward-active native BJTs add independent collector-to-emitter and base-to-emitter shot sources 2qIc and 2qIb from the selected bias currents. Native Shockley diodes contribute independent forward and reverse carrier-stream shot powers 2qIs[exp(V/VT)+1], including nonzero equilibrium noise. The same junction is not given an additional thermal-noise source. Optional resistor 1/f declarations add Ki·IDC²/f as an independent source at the frozen branch bias; require a finite positive lower frequency and do not infer a measured material spectrum. Ideal inductors, admitted conservative local dλ/dI stores and algebraic ideal transformers add no noise sources; explicit winding/core loss resistors retain their thermal noise. Generic finite-gain and powered dominant-pole amplifiers propagate these external sources in differentiable regions, but add no intrinsic amplifier noise. Their output-resistance parameter is not an extra passive resistor-noise source. Source resistance, feedback and loading remain in the network; independent contributions add in power. Solver stabilizers add no physical conductance or noise.

Single-frequency input referral uses the selected independent source: voltage inputs report V/V transfer and V/√Hz; current inputs report signed transimpedance in Ω and A/√Hz, following positive current from the source’s first contact to its second. Ideal external capacitors use j·2πfC; admitted native Q(V) stores use local dQ/dV strictly inside their voltage range. Neither adds an independent noise source. This local quasi-static propagation does not establish measured broadband material noise or loss. Transfers use the exp(+jωt) convention. Complex signal/noise transfers and magnitude-based input referral are evaluated at the selected frequency. Single-frequency mode reports density. Finite-band output mode disables the input selector and reports output RMS only. Output and input-referred band mode instead requires an explicit input and integrates output PSD divided by that frequency’s squared transfer magnitude. Voltage-input results use V RMS and V²; current-input results use A RMS and A². The current native model still requires an independent DC test source. Finite-band mode integrates output power from checked frequency estimates, one response at a time, without advancing simulation. Independent source powers are integrated separately and added before taking the square root. It never divides the completed output RMS by a gain at one frequency. A zero or nonrepresentable transfer/referral stops the input-referred band without publishing a partial result. Adaptive quadrature targets estimated integrated error of 0.01% for each independent source, with at most 4097 accepted frequencies; its error estimate does not certify sharp-feature resolution or stability. Repeat with a finer initial grid to inspect resolution. Cancel drains the outstanding read-only estimate and sends no further frequencies. The accepted point must satisfy DC bias, so a charging transient can be refused. Supported devices are resistors, ideal capacitors/inductors, conservative nonlinear flux stores strictly inside their DC range, algebraic ideal transformers, admitted native Q(V) stores at an interior DC bias, wires, ideal DC voltage/current sources, noiseless linear controlled sources, generic amplifier local laws away from rail/current-crossover corners, native MOSFETs strictly inside strong-inversion saturation, native JFETs with reverse-biased gates and forward saturated channels, forward-active native NPN/PNP BJTs with positive collector/base currents, and native Shockley diodes (excluding LED, avalanche and original CircuitJS diode models). Unsupported devices or bias regions are reported. Default temperature, individual resistor temperatures and coefficient affect this estimate only; they do not change electrical bias or simulate temperature dependence of device parameters. Frequency changes reactive propagation; local device derivatives and white source parameters stay frozen. This does not establish a high-frequency transistor model. The declared channel coefficient applies to admitted MOSFETs and JFETs; it does not calibrate a physical process. MOSFET cutoff, triode and saturation-boundary biases are refused. Their ideal insulated gate adds no shot noise; no body-junction, induced-gate or correlated channel/gate noise is included. The explicit Poisson photocurrent source adds independent one-sided 2qI noise from its nonnegative carrier mean, including a zero contribution at zero illumination. Its deterministic transient shows the mean only. A separate dark-current junction and detector capacitance must be drawn; neither is implicit in that source. BJT shot noise follows the selected bias currents; diode shot noise follows the selected bias voltage and fixed Is/VT. Neither follows the declared resistor-noise temperature. No intrinsic semiconductor flicker, intrinsic voltage/current correlation, intrinsic junction capacitance, automatic infinite-band integration, calibrated device specifications or ratings are included. A zero input transfer leaves input-referred density unavailable. Accepted-point mode needs a settled accepted point after an edit. Isolated DC mode solves a private point from the current definitions without accepting live source targets or charging stores. Estimate explicitly.

Timing capture is waiting for the workbench.

Start a raw capture with CH1 on data and CH2 on clock, advance, then Freeze.

Records up to 65,536 actual accepted points, then freezes. Start replaces the previous capture and applies its reference draft. Both timing channels subtract that socket voltage at the same accepted point; scope node voltages remain unchanged. An unbound reference is refused. Probe, circuit or reset changes retire the capture. Each recognized clock crossing occupies a sample-time bracket. Finite intermediate clock voltages widen that bracket; missing clock samples break continuity. Data activity anywhere in the bracket remains unresolved. Meets observed qualifies these samples and declared bands only. Unobserved pulses, metastability and manufacturer setup/hold guarantees require separate analysis. No scope envelopes or averaged audio bins are used. Analysis changes no circuit parameter or accepted time.

Enter two expressions, then Compare.

Use uppercase A–H, constants 0/1, NOT !, AND &, XOR ^, OR | and parentheses. Precedence: NOT, AND, XOR, OR. Every assignment of variables used in either expression is tested, with A before B and the first listed variable as the most significant bit. Up to 256 assignments, 256 ASCII bytes per expression and 32 nested parentheses/NOT operators are supported. No implicit AND or host-language evaluation. These are abstract binary values, not measured voltages or delay, drive, threshold or logic-family guarantees. The tool changes no circuit parameter.

Restart paused uses the workbench Reset state and pauses before any following interval. Begin at an accepted transient point, then Run or Advance. Each later accepted interval contributes its endpoint voltage with its actual duration as weight; the starting point is excluded. Scheduled controllers can contribute several inner electrical intervals per Advance. Total RMS includes DC; AC RMS removes the weighted mean. Min/max and ripple describe sampled endpoints, not between-sample extrema or instrument bandwidth. Missing data invalidates that channel's whole window. Control edits are included; no stationarity is assumed. Stop retains a partial record. Reset, Load, Apply or moved probes clear or invalidate it. Beginning, stopping and clearing never advance the circuit. This is calculation precision, not a physical accuracy specification.

Both channels are relative to circuit zero. CH1−CH2 subtracts the displayed accepted values; a nonfinite difference is unavailable. JSON schema 2 adds this difference as a decimal string or null. Values retain round-trip numerical precision; extra digits do not establish physical accuracy or uncertainty. After a control edit, Advance before recording its new result. Labels are your annotations. Records survive Reset and lesson loads until Clear or page close. At most 256 points are retained, with no automatic recording or replacement. JSON stores numeric values and context counters as decimal strings.

Select one uniformly spaced, stationary record table.

Uses copies of manual raw records or the displayed sinc³ history; it does not record, advance or change the circuit. For sinc³, select rows from the currently displayed history (up to 64); rows roll as new outputs arrive. The fit uses declared output cadence anchored at the first stored support center, while preserving the original stored timestamps and filter definition in JSON schema 2. No raw probe values or accepted counters are invented from filtered data. Stored centers must agree with this fit grid within 1e-8 of an output interval; this numerical allowance is not a hardware jitter bound. Select a single lesson load/build and unchanged probe sockets. For manual raw records, accepted counters and electrical times must increase uniformly. Every selected sinc³ output must have two available finite channels. Your experiment must keep its circuit and signal declarations stationary during each table; live control changes are not inferred from recorded values.

The tone must occupy an integer bin across count × sample interval, strictly above DC and below Nyquist. Cadence uses endpoint spacing and admits ordinary timestamp rounding, bounded to at most 1e-8 of one interval; this numerical allowance is not a measured clock-jitter bound. No windowing or incoherent fit is supplied. C and S are relative to the first selected record, and peak is hypot(C,S). Residual RMS includes other tones, startup and numerical errors; it is not a noise floor, ENOB, uncertainty or physical accuracy specification.

Keep a wanted-only reference before analyzing another run. Comparison requires the same sample source/filter definition, first fit-grid time, cadence, count, frequency, lesson and probe sockets; loads/builds may differ as your explicit experiment. It subtracts cosine and sine coefficients before taking a magnitude. Retained source records and declarations are exported with both fits. A smaller total peak can hide cancellation and does not establish interference rejection. A retained reference stays fixed until replaced or forgotten, even if manual records are cleared or new records arrive.

Enter one settled output voltage for every code, in ascending order. This analyzes a static DAC transfer; it does not infer ADC thresholds, missing codes, settling or hardware calibration.

To copy records, first label and record code 0, code 1, … through the full-scale code, consecutively. The last 2^N records must share one lesson load and the same probe socket. Parameter edits may change build identifiers; those edits are your declared experiment. Imported records are copied with their context into the analysis export. Recopy to use later records.

Enter a complete code table or copy labeled voltage records.

For codes 0…M, endpoint slope s=(yM−y0)/M. Offset is y0−nominal zero; gain error is s/nominal LSB−1. Nominal transfer error includes offset and gain. Nominal differential error is Δy/nominal LSB−1. Endpoint DNL is Δy/s−1; endpoint INL is (yk−y0−ks)/s. Endpoint INL is exactly zero at both endpoints. State the convention before comparing results.

Your error bound u applies independently to every entered voltage. Slope bounds are s±2u/M; residual and step bounds use at most ±2u and conservatively divide by positive slope bounds. Shared-endpoint correlations are not tightened. A step is increasing or decreasing only when its sign survives ±2u; otherwise it is unresolved (or exactly flat when u=0). A nonpositive or unresolved total span refuses endpoint normalization. Nominal references are treated as exact declarations. These ordinary floating-point intervals are not certified outward-rounded bounds. Zero u means no added error allowance, not proof of physical accuracy; RMS noise is not an absolute bound.

Compare your declared model and limits. This standalone calculation does not read or edit the circuit. Source labels are your declarations; they do not verify a device specification.

Load or edit a declaration, then compare.

Typical example

Conditional DC envelope

Declared population

Finite-band RMS noise

Enter each known bound explicitly. Blank and RMS-only declarations remain unestablished.

This is an ideal unipolar quantizer calculation, not a reading from the circuit. The example bounds and conversion duration are declarations; the noise-free two-bit teaching front end does not measure them. Every bound must apply over the stated input/reference range and acquisition/hold/conversion conditions; this tool does not derive it from R, C or a noise spectrum. Supplied peak error bounds add without assuming cancellation or independent RMS statistics. No noise draw, ENOB, confidence or hardware guarantee is produced. An interval that reaches outside the minimum reference range has no applicable complete quantization bound here.

The reference may vary anywhere within its absolute bound. Reconstruction uses its nominal value. The tool includes both the larger worst-case quantization spacing and a separate reference decode error. Do not apply this ideal bound automatically to the finite loaded SAR ladder; keep its actual measured thresholds and settling history. Outward arithmetic can leave a boundary unestablished.

Acquisition and conversion are sequential entered durations, with no pipelining, overlap, transport frame or clock uncertainty inferred. Virtual CPU dispatches and electrical Steps are not a device timing specification. The existing ADC budget panel separately covers a centered tone, continuous-RC tracking, aperture, serial framing and power.

Enter a complete candidate declaration, then Compare.

Standalone single-tone calculation; it neither reads probes nor edits the circuit. Peak amplitude is relative to the range center and must fit within half the span. Bits specify the selected mathematical quantizer, not measured ENOB or a source-module width policy. Quantization, continuous-RC acquisition/tracking, bounded aperture-time error and your other absolute error allowance add as peak bounds. RMS noise is not a peak guarantee.

The RC starts anywhere within range. Its initial error decays as span × exp(−T/RC); bounded tone slew adds 2π f A RC × (1−exp(−T/RC)), capped by the span. Aperture error is bounded by min(2A, 2π f A × time error). This is a continuous first-order envelope, not the workbench’s backward-Euler grid response. Source resistance includes the switch; capacitance is linear. Aperture error shifts sampled signal time while acquisition duration and the resource schedule stay fixed; uncertain durations need separate worst-case timing declarations. Charge injection, nonlinear settling and calibrated device errors are not inferred.

Every sample uses a sequential acquisition + conversion + complete frame. Include command/address/framing/CRC/padding in frame bits; no overlap, batching, retries or clock tolerance is assumed. Strict sample rate > 2 × tone frequency is necessary here and does not establish anti-alias filtering for other signals. Power is your declaration; include all loads required by your budget. Positive margins and passing checks describe these entered assumptions, not hardware qualification or a vendor recommendation.

Enter a declared DC point and limits, then Compare.

Allowed power stays at the declared full value up to the first endpoint, falls linearly to zero at the second, and stays zero above it. The DC magnitude limit is the smaller of √(allowed power × resistance) and the separate voltage ceiling. Temperature changes this rule, not the circuit resistance. This comparison does not evaluate operating-temperature range, pulse energy, mounting or part validity. Markings and package size do not supply these declarations. Reference: KOA resistor fundamentals.

Choose the scheme from the part documentation, then Decode.

Use lowercase color names separated by spaces: black, brown, red, orange, yellow, green, blue, violet, grey (or gray), white, gold, silver. Supply the reading direction; the decoder does not reverse bands. Three bands use two digits, multiplier and an absent tolerance band (20%); four add tolerance; five use three digits; six add the chart’s temperature-code magnitude. Numeric examples: 472 = 4700 Ω, 4700 = 470 Ω, 4R7 = 4.7 Ω. Numeric codes do not establish tolerance. The separate Bourns CR0603 EIA-96 table uses indices 01–96 and uppercase A–H, X, Y or Z multipliers: 01C = 10 kΩ, 68B = 4.99 kΩ. Its declared 1% tolerance comes from the selected table, not the number of printed digits. R/S aliases and lowercase letters are refused. A table combination does not establish that a part is orderable. Other vendor conventions require their own documentation. Symbols do not identify a package, pin numbers, power/voltage/current rating or a signed temperature-feedback law. This tool changes no circuit parameter. Bourns CR series marking reference.

Band reference: Vishay chart 20143, revision 28-Aug-09; brown/red temperature codes depend on the model.

Choose the convention from the part documentation, then look up its code.

This is a scaled diagram, not actual screen size. Nominal codes are rounded identifiers: do not convert their digits as exact inch measurements. The same code can mean different sizes in different conventions. Alternatives and aliases are retained where the reference supplies them. Body dimensions do not define pads, terminal dimensions, height, mechanical tolerances, polarity, pin numbering or electrical ratings. A size code is not a resistance value. This lookup changes no component or breadboard geometry; use the exact part drawing and recommended land pattern.

Reference: KOA flat-chip size table. Outlines use its reported L × W, including wide-terminal orientations.

Read from the marked top, with the lone lead at the top in the initial view: pin 1 is lower left, pin 2 lower right, pin 3 above. Rotation moves leads without renumbering them. A bottom view is mirrored; this control only rotates a top view. The two parts share numbered positions but have different terminal functions. Select the exact manufacturer and part before using a pin map.

This schematic has no mechanical scale, pads or land pattern. Marking templates are documented examples, not unique identification or authentication of an unknown device. The % character stands for a manufacturing-site code, not a literal percent printed on every part. Other manufacturers and suffixes require their own datasheets. These references change no circuit, model, pin mapping or breadboard footprint, and supply no electrical rating or vendor calibration.

Pause a static native DC circuit, choose resistors, then Analyze.

Analysis uses configured targets, which can differ from the last accepted readings after a live edit. Fresh DC solves never edit the live circuit or advance time. Endpoint mode enumerates up to eight low/high selections (256 configurations); uniform modes integrate an explicitly assumed uniform error interval using equal-weight midpoint cells (up to 1024 configurations). Independent grids use every cell combination. Tracking uses the same fractional error for all selected resistors; opposed mode uses opposite errors for a pair. These are deterministic quadrature estimates, not random samples, standard errors, time-varying noise or inferred device distributions. Refine the grid to assess numerical convergence. Mean error is relative to the configured nominal, not an external design target.

Sampled extrema are not guaranteed global bounds for arbitrary active/nonlinear networks. A failed solve refuses the whole report rather than omitting a configuration. Static native resistors, DC sources, potentiometers, diodes, transistors and algebraic amplifiers/controlled sources are supported; storage, time-varying/driven sources and stateful/imported devices are excluded. A monotone divider has a separately provable endpoint bound; midpoint grids do not include those endpoints.

Select a documented convention; these fields do not identify arbitrary body marks or complete part numbers.

Decode is read-only. The same digits can use different units. An absent tolerance remains unknown; a code is not a current rating, saturation curve, package, technology or proof of availability. Coilcraft CPS dash-number convention · Murata LQ part-number fields 6–7.

Choose the documented convention before decoding. Letter case matters.

Numeric pF fields use two significant digits and a power-of-ten digit, or a middle R decimal point; only an explicit J/K/M suffix supplies tolerance. Option M uses V, a case-sensitive letter and a listed multiplier; it supplies no tolerance. Option Q uses a separate Vt prefix, a space and the numeric pF value: absolute pF and percentage tolerance are different units. These symbols do not identify a part, dielectric, voltage rating, polarity, pinout or package dimensions. Missing and unmarked parts are not guessed. Decoding leaves the circuit unchanged.

References: Vishay 45028 · options M/Q, pages 1–2; Vishay 45171 · numeric fields and tolerance, page 2. Other series and marking options require their own documents.

Pause an ordinary native circuit, choose an input source and connected output, then Analyze.

Each point solves the current linear RLC, wire, controlled-source and ideal-transformer network using exp(+jωt). A voltage input has a 1 V peak phasor from its first contact to its second; a current input has 1 A peak from first to second. All other independent sources have zero AC excitation. Linear-mode excitation ignores authored waveforms and DC levels. DC-biased mode uses the configured DC levels to determine local device derivatives. Reactive initial conditions do not define the isolated DC bias or AC excitation. Voltage transfer is V/V; current-input transimpedance is Ω. No transient step is taken. Linear mode needs no bias; DC-biased mode solves its own isolated operating point. Its unit normalization is a local derivative, not a finite 1 V or 1 A device excursion.

Pause before starting. Probe/circuit changes clear old results. Stop drains the outstanding read-only point and sends no further requests. The graph samples frequencies, not every value between them. Phase is wrapped to −180…180° with breaks at wrap crossings; zero calculated transfer has undefined phase and −∞ voltage gain in dB, omitted from the corresponding plotted trace. Linear mode does not linearize nonlinear devices. DC-biased mode admits the declared native semiconductor models and generic finite-gain op amps and powered regulators in smooth regions; active model corners are refused. The regulator is quasistatic, with frequency dependence supplied by external components. The generic op amp retains implicit supply power and has no intrinsic bandwidth or slew rate. Admitted native Q(V) stores use their local dQ/dV strictly inside the declared voltage range; this does not validate broadband material behavior. The stateful five-contact powered amplifier includes its declared internal dominant pole in smooth isolated-DC AC analysis; active rail, supply and current-crossover boundaries are refused. Sampled controllers, original CircuitJS profiles and thermal feedback owners remain excluded. Group delay is the local continuous −d(phase)/dω in seconds, calculated by differentiating the same circuit equations, not by subtracting wrapped phase samples. It can be negative and is undefined at calculated zero or a nonrepresentable normalized slope; near a transfer zero both phase and delay are ill-conditioned. It describes narrowband envelope timing, not phase delay, startup or settling, and does not predict the finite-step scope delay. A frequency solution does not prove stability or decaying startup in an active network. These mathematical linear models do not establish bandwidth or rating guarantees for real parts.

Evaluate small-signal capacitance tables at their declared measurement frequency and amplitude. Review the source and conditions before interpreting an interpolated value.

Load the example or paste a complete source declaration.

Each raw table contains one temperature slice, using degrees Celsius, volts and farads in the example’s CSV schema. Slices need increasing temperatures, a common DC-bias axis, and the same specimen, measurement frequency/amplitude, conditioning and topology. Queries stay inside the supplied range. Source metadata and guarantees are declarations, not authenticated measurements. Interpolation preserves source-row weights and raw-data identities. This is data analysis: it does not change the circuit, infer a quasi-static Q(V) law, or establish stored energy, material accuracy or device ratings.

Means for calculation await a completed accepted block.

Twelve significant digits from the same completed block shown above. Extra digits retain numerical precision; they do not establish measurement accuracy.

Sinc³ awaits accepted samples.

Three cascaded length-256 moving averages act on raw accepted probe voltages before every 256th output. Full FIR support is 766 samples; no zero padding is used. The first output is after 768 accepted samples, then every 256. Missing/nonfinite input marks its channel unavailable throughout the affected support. The other channel remains independent. History clears on probe, grid, clock discontinuity and circuit reset/rebuild changes.

Centered signed gain is [sin(256π f/fs)/(256 sin(π f/fs))]³, with unity DC. Group delay is 382.5 input intervals. This changes passband droop and alias rejection and adds latency; it does not change the physical circuit or the feedback bit sequence. Source, decision-clock and decimated rates are distinct. Compare each output with its own support-center time. Neither averaging nor a filter null establishes ADC accuracy, a noise floor, ENOB or a complete anti-alias specification.

The bounded moving-average realization avoids unbounded integrator registers; it is not a fixed-width hardware CIC implementation. Periodic compensated-sum rebasing limits accumulated rounding drift. Export copies the displayed full-precision numeric history with probe labels and exact load/build identifiers; it does not promise a newer server frame or save circuit state.

Generate a new physical circuit, then use the native file panel to Inspect and Load it.

Q0 is the least significant bit. On each common rising edge, s_next = ((s << 1) & (2^width − 1)) | parity(s & taps). A mask bit selects the corresponding old Q output for the feedback XOR. A balanced tree of XORs with at most four inputs implements parity. Every memory, gate, tap contact, load and RC part is an actual editable component. Each Q has a 10 kΩ load; Q0 also feeds a 10 kΩ/1 µF RC. Outputs are ideal 0/5 V, and the requested grid has 128 intervals per clock. This is a new cold design; staging and downloading leave the current circuit unchanged. Inspect the generated file, then explicitly Load whole design to replace it.

Try width 3 / taps 6 / seed 1 (7-edge cycle), width 4 / taps C / seed 1 (15), or width 8 / taps B8 / seed 1 (255). Width 8 / B0 gives 93 edges. Zero seed locks at zero. Zero taps with seed 1 shift into zero after width edges. Width 16 / B400 / seed 1 predicts 65535 edges, beyond the 1024-word history. These values use the stated shift direction and bit numbering; tap tables using other conventions may differ.

The bounded integer census reports a transient prefix and eventual cycle for the declared seed. It does not drive the physical register or certify random noise, security, vendor logic or hardware timing. Without the highest tap, transients can precede the cycle. Use actual Clocked words and Decision bits after loading; the current history can compare two complete blocks only through 512 edges. All-zero and single-tap masks keep a literal XOR with extra ground contacts.

No mapped design staged by this panel.

Exact sixteen-row Boolean enumeration removes inessential inputs. Each output must depend on at most two independent signals; a three-input function is refused. The generated 38-part circuit uses actual mux, register and external configuration contacts. This is a bounded Boolean mapper, not HDL synthesis, a vendor bitstream, physical configuration storage or timing closure. Generation/staging/download do not change the current circuit. Inspect and explicitly Load the whole native design to use it. Later direct circuit edits do not recompile or rewrite its source notes.

Analyzes the source currently typed in the equation mapper. Bounds below are declared hypotheses in ns, not measured cell parameters or the literal simulator's propagation timing. The simulator and staged native files are unchanged. Both registers are analyzed even in output bypass.

No declared timing report.

All clocks share one period; arrivals are branch insertion delays from reference edge 0. A/B arrival bounds are meaningful only under the explicit synchronous assumption. Setup uses the next capture edge; hold uses the same edge. Positive capture skew helps setup and hurts hold; a slower clock does not fix hold. Input-route and LUT delays feed D; the output mux affects OUT only. Configuration stays fixed. Reset recovery/removal, jitter/uncertainty, clock-domain crossing, analog hazards, supply/thermal variation and real hardware timing closure are not certified. A constant/no-path result is not a startup guarantee. Output windows are conditional on a logic change and are not simulated timestamps. Editing inputs leaves the prior copied report labeled as stale.

Clocked words await a shared-clock bank of 2–16 flip-flops.

Reads actual post-edge Q voltages from all 2–16 D flip-flops when they share one clock node and HIGH voltage. Bit zero is the first flip-flop in circuit element order when configured; topology transport preserves that bit order and labels identify every bit. A rising edge crosses strictly above half HIGH voltage. The first accepted HIGH clock counts as an edge. This observer neither generates words nor changes the physical circuit. History clears on runtime reset or circuit rebuild; probe changes do not alter the bank.

The repeat report finds the smallest word block repeated across the entire retained history, requiring at least two complete blocks. It is a finite observation, not a proof of future period, independence, randomness or hardware timing. Startup or a changed sequence may prevent a repeat report. Edge counters are exact decimal strings in JSON. Export copies the displayed history and load/build identifiers.

Select two matching full word blocks from displayed clocked history.

Analyzes a fixed copy of two adjacent matching word blocks from one captured lesson load/build. Every full word must match, not only the chosen bit. Accepted edge times must be uniformly spaced and numerically resolved. It does not record or advance the circuit. Displayed history rolls at 1024 words; row selections refer to the currently displayed history. New captured rows do not change a completed analysis; Analyze again to copy a newer selection.

For the first selected block of N decisions, z = 2 × bit − 1. Circular raw correlation at lag ℓ is Σ z[j] z[(j+ℓ) mod N] / N; no mean is removed. Z[k] = Σ z[j] exp(−i2πkj/N) / N, with phase origin at the first selected edge. The table shows nonnegative bins only; negative-frequency coefficients are complex conjugates. An even N includes Nyquist; an odd N does not. HIGH coefficient fraction is the magnitude for a 0/1 bit: DC is the HIGH fraction, and other bins are |Z|/2. HIGH peak fraction doubles paired bins, but never DC or Nyquist. Multiply fractions by the ideal HIGH level only for a declared 0/HIGH decision model.

A requested block may contain a smaller circular word or bit period; both are reported separately. Matching two finite blocks does not prove future repetition, independence, unpredictability or a noise density. These are decision-bit coefficients, not the oversampled held-voltage spectrum, an analog PSD, measured jitter, SNR or converter accuracy. Timestamp admission allows ordinary floating-point rounding; it is not a hardware jitter bound.